ADVISE: Performance Evaluation of Parallel VHDL Simulation

VHDL is the one of the most important and widely used hardware description languages at this time. The increase in size and complexity of VHDL models necessitates the use of parallel and distributed algorithms to obtain acceptable simulation performance. We have investigated the use of optimistic distributed algorithms with VHDL simulation. Using an optimistic algorithm with VHDL introduces some major problems which can only be solved at some cost. With our simulation environment we obtain speedups of around four for a medium-sized benchmark. We expect that the optimisation of our environment and partitioning, and the use of larger benchmarks will lead to higher speedups, which makes it worthwhile to investigate this approach further.